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Final Design Goals

Drawing Opps Required

My initial approach was to implement all of the above in specialized hardware units.  However, due to the simplicity of writing shader programs, it is likely that most of the above will be handled in firmware.  I am not sure if there will be an advantage in size or power to keep specialized functional units in the TVC.

Anti-aliasing will be done at the whole display or rendering window level, not at the entity level.

Performance Increases

Some back of the envelope calculations with a dull crayon follow. These numbers are based on TVC release #5's pure firmware/software implementation. I tried to lean toward conservative estimates. These numbers assume moving to an artix7 XC7A200T, and again no specialized rendering units.

20x More Cores
4x Hardware FP Support
1.5x Vector Opps
3x Clock Speed
1.5x Compiler Optimizations

Design Abstractions

TVC development has proceeded based on the abstraction that a video card is composed of four components.  These components are: #1 a large block of memory used for the frame buffer, depth buffer, textures, commands, etc.,  #2 a display module that pushes pixel values to an external display, #3 a communications link to a host processor and #4, a block of drawing functional units driven by the host that perform drawing operations by reading and writing to the large block of memory.

Most of the complexity specific to a video card is in the block of functional units.  The functional units may be developed largely independently of each other, provided all components are designed around common internal interconnects.



Not Going To Do

Fix the bugs in the mcu-hl.
These bugs are likely the cause of the missing/incorrect pixels in the teapot test.

Reason: After playing with the design of a sdram controller, I realized that the current design of TVC is quite tied to the current memory controller, and the addition of the DQM (data mask lines) in sdram makes a tremendous amount of complexity in the MCU-HL obsolete and irrelevant.  The entire memory controller needs to be ripped out and replaced (which will mean I need a different development kit).  This change will ripple changes into the MU bus design.